The graph below shows SRAM scaling trend from 180nm logic node down to bleeding edge 3nm. Due to challenges in Moore’s law scaling, SRAM density slowed down starting at around 10nm and officially stopped scaling going from 5nm to 3nm.
Industry is urgently trying to find a workaround, with options ranging from hybrid bonding of SRAM chiplets on top of compute die (e.g. AMD 3D V-cache) to exploring new memories like MRAM.
Data source:
[1] https://semiwiki.com/forum/index.php?threads/tsmc-officially-halts-sram-scaling.17223/
[2] https://ieeexplore.ieee.org/abstract/document/8268472
The views expressed here are the authors’ own.